Resistive memories of the OxRRAM type (acronym for “Oxide-Based Resistive Random Access Memories”) typically comprising a metal oxide layer, are preferentially chosen for non-volatile applications, with the purpose of replacing memories of the Flash type. They in particular have the advantage of being compatible with the end of line method (acronym BEOL for “Back-End Of Line”) of the CMOS technology (acronym for “Complementary Metal-Oxide-Semiconductor”).
OxRRAM resistive memories are devices that in particular include a metal oxide layer arranged between two electrodes. The electrical resistance of such devices can be modified by write and erase operations. These write and erase operations make it possible to switch the OxRAM resistive memory device from an LRS (acronym for “Low Resistive State”) to an HRS (acronym for “High Resistive State”), and inversely.
During programming steps, i.e. when sufficient voltage and current are applied to the device, with a limitation for the current passing through the device, less, for example, than a few milliamperes (mA), conductive filaments can be created selectively (LRS state) and be broken (HRS state) between the electrodes through the oxide layer.
From cycle to cycle, the resistances of the low resistance LRS and high resistance HRS states tend to change. A variability in these LRS and HRS resistances is therefore observed during the life of these memory cells.
This variability is also observed from cell to cell.
This variability is particularly substantial for the high resistance state HRS, inducing a decrease in the programming window, even a total loss of the programming window. This variability problem is today a real barrier for industrialization.
This concern remains despite many efforts made in the field of methods for manufacturing resistive memories and programming methods.
Moreover, many studies have been conducted in order to reduce the variability of the electrical performance by reducing the contact surface between one of the electrodes and the oxide layer.
In particular, it has been shown in the publication: “Conductive Filament Control in Highly Scalable Unipolar Resistive Switching Devices for Low-Power and High-density Next Generation Memory”, Kyung-Chang Ryoo et al., IEDM2013, that a solution for reducing the dimensions of the device is to reduce the contact surface between one of the electrodes and the oxide layer. This solution involves complex and expensive methods of implementation.
Document U.S. Pat. No. 8,470,681 proposes to add a disturbing element in the oxide layer and on the lower electrode, in such a way as to favor the forming of a conductive filament on the zone where the disturbing element is located. The adding of this element generates a field of constraints that are more substantial in the device. In this same document, another embodiment consists is creating a shape of a cone or pyramid in the lower electrode, before proceeding with the deposition of the oxide layer.
These solutions have for disadvantages to add many steps in the manufacture of the device. Moreover these steps are complex and it is not easy to achieve good reproducibility.
Moreover, the reduction in the surface of the upper electrode renders tapping complex on this electrode.
Document FR2998708 proposes to minimize the dimensions of the memory point formed by the material inside of which the conductive filament is created between the two electrodes of the memory cell CBRAM. The invention primarily relates to 37 ionic conductive memories (CBRAM memories or “Conductive Bridging RAM”, but can be extended to other types of memories. It requires several levels of lithography. One of the technological sequences proposed is the following: creation of a metal line, creation of an inert lower electrode, for example, via a damascene method, creation of a confinement electrode comprising a soluble material, deposition of a dielectric, creation of an additional via by lithography, creation of spacers (deposition, etching), filling with a material, chemical-mechanical polishing, then another deposition of a dielectric layer, creation of a via by lithography, creation of spacers and filling with a material. The objective is to create a point effect on the upper electrode, but to retain a sufficient volume of electrolyte (CBRAM applications). Document U.S. Pat. No. 8,377,789 aims for the same objective be seeking a point effect on the transition metal oxide.
Disadvantages appear in this type of device. First of all, problems can arise during the filling of via, in particular when aiming for minimizing dimensions. Moreover, the method for manufacturing such devices is difficult to implement in terms of technological production and reproducibility.
As such in all of the known solutions, in order to form a reduced contact surface between at least one of the electrodes and the oxide layer, it is necessary have recourse to multiple and therefore expensive steps. In particular, the steps of lithography, of deposition, of planarization, required in order to obtain nanometric dimensions on contacts between the electrodes and the dielectric material of the oxide layer are complex and require complex development steps that are not always perfectly reproducible. Moreover, a tapping carried out on a small surface inevitably results in additional constraints on industrialization.
This invention aims to overcome all or, at least, a portion of the disadvantages of current techniques. It would be in particular advantageous to propose a solution to reduce, even suppress, the variability in the HRS and/or LRS resistances observed cycle after cycle for resistive memory devices, while still limiting or avoiding the disadvantages of the known production methods of prior art mentioned hereinabove.